A common form of electronic subsystem includes a printed circuit board (PCB) with multiple packaged components assembled onto the board, wherein each packaged component includes a semiconductor chip or die. As the clock rate of electronic subsystems has increased, it has become desirable to make smaller and smaller packages. The smaller packages typically have shorter lead lengths with lower inductance, and the lower inductance enables higher speed operation. Flip-chip packages represent an extension of this trend, comprising bumped die directly attached to a package substrate or PCB. The bumps have typically been solder balls arranged in ball grid arrays (BGAs).
BGA attachments are quite rigid because the solder balls are essentially rugged little spheres composed of strong bonding material. The attachment between chip and substrate comprising an array of such spheres is stiff rather than compliant. Since semiconductor materials expand and contract at slower rates than typical substrates, temperature excursions cause shear forces to develop at the interface between chip and substrate. These temperature excursions occur during both manufacture and operation. The shear stresses may cause buckling, cracking or de-lamination. This aspect of semiconductor packaging has been much described in the literature. In practice, BGA attachments using solder balls only work satisfactorily for die sizes up to around 3 mm on a side, unless an epoxy under-layer is used to help bind things together. However, if an epoxy under-layer is used, it is almost impossible to rework an assembled die that proves to be defective.
A typical microprocessor chip has an edge dimension of around 18 mm. For assembling this larger die using flip chip attachments (and avoiding an epoxy under layer) an improved flip chip connector is required. This improved flip chip connector will preferably have flexible connections that are compliant enough to absorb the maximum shear stresses that can occur.
The flip chip connectors attach to input/output pads on the front side of an IC chip. The back side of the chip typically requires attachment to a heat sink; especially for microprocessors that dissipate 100-150 watts (W) of heat today, and are projected to dissipate nearly 500 W by 2010. The heat sink is typically constructed from a good heat conductor such as copper, and copper has similar expansion properties to glass-epoxy laminate materials used as PCB substrates. Thermal grease has been used at this interface. It conducts heat between chip and heat sink, yet allows them to slide against each other to relieve shear stress. However, thermal grease is not conductive enough to meet the heat-sinking requirements projected for 2010. Accordingly, a new device called an interface adaptor has been proposed for attaching the semiconductor substrate to the heat sink. The interface adaptor has flexible copper fingers that are thermally conductive and can absorb lateral displacements (shear stresses); such interface adaptors are included in the preferred embodiment of the current invention. The details of construction and manufacture of these interface adaptors is described in co-pending U.S. patent application Ser. No. 10/997,566.
Wafer level packaging (WLP) is a recent manufacturing strategy. It extends the economies of scale inherent in wafer manufacturing to include elements of the packaging solution. It will be shown that the preferred flip chip connectors of the current invention can be fabricated using wafer level processes; the same is true for the proposed interface adaptors. A typical microprocessor chip measures 18 mm on a side and 177 of them fit on a 300 mm wafer. At 90% yield, 159 will be functional. In this case the proposed additional back-end wafer fabrication costs are spread over 159 good die.
A popular series of mask aligners for wafer level packaging work is manufactured by Suss MicroTec AG based in Munich, Germany. These are full field proximity aligners and include the MA300Plus for 300 mm wafers. This aligner is primarily designed for exposing semiconductor wafers. However, it can also be used to expose square substrates of similar thickness. For fabricating the high-performance cables of the current invention the preferred substrate is a 300 mm square blank of cold rolled copper having a thickness of 400-800 μm.
New processes have been developed by Eugene M. Chow et al. for polysilicon based through-wafer interconnects (polysilicon feedthroughs) in silicon substrates: “Process Compatible Polysilicon-Based Electrical Through-Wafer Interconnects in Silicon Substrates”, Journal of Micro-electro-mechanical Systems, Vol. II, No. 6, December 2002. The feedthroughs are produced in wafers 400 μm thick and have a diameter of 20 μm. Each feedthrough has a series resistance of 10-14 Ω, and less than 1 pF capacitance. The fabrication process employs high temperatures, and the finished wafers are “process compatible”; this means that they can be subsequently processed to produce active and passive devices using conventional fabrication methods. Wafers fabricated in this manner are preferably used in the current invention to produce input/output (I/O) plugs, as will be further described.
New alignment methods have been developed for pick and place machines, for accurately placing die on substrates employing flip-chip attachments. One such method known in the art uses split-beam optics and achieves an alignment accuracy of ±1 μm.
Three dimensional semiconductor assemblies have been produced in several forms. One popular form is a “stacked die” approach for producing a system in package (SiP). Typically the stack includes one chip per layer. Although either flip chip or wire bond connections can be used, the majority of stacked die arrangements have used wire bonds. With wire bonding, the bonding pads are typically available only at the chip periphery; not in area arrays as for typical flip chip. This limitation severely constrains how wire-bonded chips can be combined; the pad order must be taken into account or else the bonding wires will cross, producing short circuit failures. Also the chip sizes in the stack are constrained in order that the bonding tool can access all of the pads. In addition, the chips must be thick enough and strong enough for making bonds on any overhanging (cantilevered) edges; the bonding action requires the application of force that is transferred from the bonding tool to the bonding surface. These factors have limited the complexity of stacked semiconductor assemblies using wire bonds to around 4 or 5 chips maximum. Also, since the bonding wires are typically long compared with flip chip connectors, the associated inductance limits the signaling speed. Conversely, improved flip chip connections of the current invention have low inductance and are projected to support signaling rates up to 10 Gbps.
Three dimensional (3D) silicon structures have also been proposed employing bonded wafer-to-wafer assemblies. R. J. Gutman et al. have described processes for aligning the wafers, bonding the wafers using low temperature adhesives, precision thinning and leveling, and inter-wafer connections using high aspect ratio vias: “Wafer-Level Three-Dimensional ICs: A Better Solution than SoCs and SiPs?”, International Wafer Level Packaging Congress, San Jose Calif., October 2004. The resulting 3D circuits have excellent electrical performance because the signaling distances from wafer to wafer are as short as a few microns. However the manufacturing infrastructure required to produce these structures is substantial. Also fundamental difficulties remain including: yield hits when any portion of the assembly is defective; lack of thermal management strategies; lack of effective test strategies; the need for stacked components to have the same area; and the need to synchronize die shrinks of stacked components. Of these limitations, the only one that applies to subsystems created using methods of the current invention is the need to synchronize die shrinks of stacked components.